In many memory systems (e.g., DDR, DDR2, DDR3, LPDDR, and PDDR2), both the memory controller and the DRAM chips share the same data bus to communicate with one another. Since data is bidirectional, each end implements both receiver and transmitter logic connected to the data bus signal.
As such, a finite amount of time is required to switch the data direction of the data bus. Further, closing an existing page within memory and opening a new page takes time. Many current systems are implemented in a way that serializes the two processes. As a result, memory commands take a longer time to execute.